The present invention relates to a direct digital synthesizer which provides a large number of tuning channels without requiring a complex and slowly operating phase accumulator.
A direct digital synthesizer is an electronic apparatus for generating a cyclic waveform from instantaneous values thereof stored in a wave lookup table or memory. The wave lookup table is accessed by a phase number address that is successively increased by a phase increment. In a typical circuit, a phase accumulator employed to address the phase lookup table repeatedly adds the phase increment to its accumulation for generating successive addresses. The smaller the phase increment, the more samples are obtained from the wave lookup table during a given output period, and the lower the frequency of the output. If the phase increment is made larger, the output frequency increases. After a complete cycle of the waveform has been accessed from the wave lookup table, the process is repeated, with the digitally stored samples being supplied to a digital-to-analog converter for generating the desired waveform output.
Direct digital synthesizers are limited in maximum number of tuning channels by the size of the accumulator employed for addressing the wave lookup table. Increasing the size of the accumulator results in reduced channel spacing and an increase in the number of possible tuning channels (i.e., providing increased frequency resolution). However, circuit complexity is increased and the rate at which the circuit can operate is reduced. The last effect is due to the longer carry propagation chain associated with a larger adder circuit forming part of the accumulator.
An example of a prior art direct digital synthesizer is described in U.S. Pat. No. 3,735,269 to Jackson. In this apparatus, used to synthesize decimal based frequency steps, a binary coded decimal adder is used to accumulate the phase. Unfortunately, there is substantial delay associated with the BCD arithmetic.
Another example is set forth and claimed in co-pending application Ser. No. 07/325,359, filed Mar. 17, 1989, now U.S. Pat. No. 4,951,004, for "Coherent Direct Digital Synthesizer" filed by Tzafrir Sheffer and Eric Drucker. This application relates to a phase locked circuit based on a binary phase accumulator. Although this approach provides a coherent output, analog components are required such as a low pass filter and a voltage-controlled oscillator, rendering the circuit more complex and less integrable into a digital IC.